Abstract

The ability to accept a little mistake is less significant than the ability to have a low power consumption a high throughput and a compact chip area of an arithmetic unit when it comes to the 3D graphic applications that are carried out on mobile devices. In comparison to the other mathematical units a divider is the one that requires the greatest effort and time to complete. For the purpose of designing and implementing a divider utilizing 0.25?m CMOS technology we use the LNS which stands for the logarithmic number system. It is possible to increase the accuracy of the result while simultaneously reducing the amount of power that is used by using a piecewise approximation approach that incorporates differential coefficients for logarithmic conversion. A comparison between our divider and the standard restoring divider reveals that the operating speed is significantly enhanced but at the price of a minor increase in the number of gates. We also demonstrate that the mistake that is br