Abstract

The rapid evolution of multicore and many-core processors has intensified the demand for efficient on-chip communication infrastructures capable of sustaining high data throughput predictable latency and dynamic performance scaling. Network-on-Chip (NoC) architectures have emerged as a scalable communication backbone that interconnects processing cores caches and specialized accelerators with reduced wiring complexity and improved modularity. A central challenge in NoC-based systems is to ensure efficient scheduling of packets across on-chip switches while meeting stringent Quality-of-Service (QoS) requirements such as bounded latency guaranteed bandwidth and fairness across traffic flows. Additionally modern workloads exhibit dynamic and unpredictable communication patterns making static scheduling strategies insufficient. As a result adaptive scheduling techniques capable of responding to varying hardware resource availability thermal constraints and runtime traffic fluctuations are